| dc.contributor.advisor | Johnson, Louis G. | |
| dc.contributor.author | Gopi, Srikanth | |
| dc.date.accessioned | 2014-04-17T20:08:33Z | |
| dc.date.available | 2014-04-17T20:08:33Z | |
| dc.date.issued | 2006-05-01 | |
| dc.identifier.uri | https://hdl.handle.net/11244/10205 | |
| dc.description.abstract | The objective of this thesis is to design a 32-bit 32-word 10-read/write port register file in the AMI 0.6 micron process and optimize the read access time, noise margin and the area occupied by the register file. A 10-port SRAM cell with infinite read noise margin was designed. The memory cell array occupies an area of 1.294 sq mm. The measured read access time of the regisiter file was 1.96ns. | |
| dc.format | application/pdf | |
| dc.language | en_US | |
| dc.publisher | Oklahoma State University | |
| dc.rights | Copyright is held by the author who has granted the Oklahoma State University Library the non-exclusive right to share this material in its institutional repository. Contact Digital Library Services at lib-dls@okstate.edu or 405-744-9161 for the permission policy on the use, reproduction or distribution of this material. | |
| dc.title | Design of 32-bit 32-word 10-read/Write Port Register File | |
| dc.type | text | |
| dc.contributor.committeeMember | Zhang, Weili | |
| dc.contributor.committeeMember | Zhang, Yumin | |
| osu.filename | Gopi_okstate_0664M_1825.pdf | |
| osu.college | Engineering, Architecture, and Technology | |
| osu.accesstype | Open Access | |
| dc.description.department | School of Electrical & Computer Engineering | |
| dc.type.genre | Thesis | |
