Design of 32-bit 32-word 10-read/Write Port Register File
Abstract
The objective of this thesis is to design a 32-bit 32-word 10-read/write port register file in the AMI 0.6 micron process and optimize the read access time, noise margin and the area occupied by the register file. A 10-port SRAM cell with infinite read noise margin was designed. The memory cell array occupies an area of 1.294 sq mm. The measured read access time of the regisiter file was 1.96ns.
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- OSU Theses [15752]