Comparative Analysis of Different Aes Implementations for 65nm Technologies

Abstract

Encryption has a strong presence in today's digital electronics with the frequent transmission and storage of sensitive data. NIST selected AES as the standard encryption algorithm and it is commonly used as a fast solution to secure data. When designing VLSI systems, the task of balancing the area, power, and speed is a challenge; hardware encryption is no different. System requirements drive certain performance parameters to the forefront, identifying how to alter a design implementations to meet performance requirements is not always apparent. Multiple resources in this research field have identified AES algorithm features of interest and discussed their impact a few of the design trade spaces, however, a single comparative analysis was lacking. This thesis explores six different AES features key size, mode specificity, round key storage, round unraveling, SBOX implementation, and pipelining. A summarized view of the resulting designs allow readers to quickly analyze how each of the six features impacts speed, power, area, latency and throughput using 65nm process.