A new method for realizing parallel processing machines using multiple-valued logic.

Abstract

Parallel processing machines that can perform two or more operations simultaneously have been constructed to provide concurrent operation of identical or highly similar system components. Currently, parallel operation is achieved by connecting separate binary logic system components. This thesis explores the application of r-valued logic for the development of logic circuits that function as m identical but independent q-valued logic circuits (r = q('m)). The resulting machine exhibits inherent parallelism wherein the logic values of the m sub-machines are multiplexed within the r levels of the multiple-valued logic, and the r-valued memory elements simultaneously store the logic states of the m machines. Multiple-valued digital circuits and systems possessing these attributes are said to be state integrated and logic multiplexed. For the case q = 2, m identical binary machines can be combined into one r-valued r = 2('m) machine that provides the same functions as m parallel binary machines. Further, given a single binary logic circuit, either combinational or sequential, m copies of the circuit can be constructed directly in a 2('m) logic system. Each bindary sub-circuit operates in parallel and independently of the other m-1 sub-circuits. To aid the sequential circuit design process, a new multiple-valued memory element is developed that simultaneously stores information for the independent binary sub-machines. Various circuit types are developed, all of which are important for the specification of a state integrated and multiplexed computer processor. A quaternary logic simulator is presented and is used to illustrate the expected operation of the various circuits.