CMOS circuit speed and power optimization using simplified RC delay model

Abstract

A simplified RC delay model which is expressed explicitly in terms of transistor widths is presented to easily perform circuit analysis and quickly optimize the transistor widths for delay and power without having to do tedious layout or schematic simulation. A novel heuristic gradient descent method is used to effectively solve the optimization problem. Popular parallel prefix adders such as Brent-Kung, Skylansky and Kogge-Stone adders are modeled using the proposed simplified RC delay model and a power-delay performance comparison is done after optimization to show the ability of the model. The optimization results suggest that the Brent-Kung adder is more efficient in terms of both delay and power by having the lowest power-delay product followed by the Skylansky adder and then the Kogge-Stone adder.