NAND flash compiler using the SkyWater 130nm Process

Abstract

NAND flash memory is commonly used for data storage, with applications in SSDs and flash drives. NAND flash research in academia can be limited by insufficient access to memory of varied sizes. This thesis discusses the design of a NAND flash memory compiler. This compiler provides researchers access to a customizable flash array. The array is built using the SkyWater Technology 130nm Process Design Kit (PDK) and SONOS flash technology. A detailed review of the implementation is included covering both the physical design of the flash array as well as the design of the compiler. The result of the compiler is able to be fabricated, as shown by an approved submission to Efabless' Multi-Project Wafer (MPW) shuttle program. The results consist of simulations that prove the functionality of the flash array.