Implementation of a Hardware Algorithm for Integer Division

Abstract

A hardware algorithm for integer division proposed by Naofumi Takagi, ShunsukeKadowaki and Kazuyoshi Takagi is implemented using the hardware-descriptive language called Verilog. The hardware algorithm is based on digit-recurrence non-restoring division. Each partial remainder is represented as an SD2 integer as a pair of its sign and absolute value. Quotient digit is obtained from the sign of every partial remainder with the most significant digit first. Quotient is obtained as an ordinary binary number and remainder as an SD2 integer. Remainder is converted from SD2 to binary using the concept of a carry lookahead adder. Combinational design for 4-bit and 8-bit integers that uses radix-2 signed-digit representation of numbers is implemented. It is simulated and tested using Mentor Graphics Corporation (MGC)® ModelSim™. RTL synthesis is performed and parameters like area, total cells, timing and power are calculated.