Efficient Implementation of Radix-4 Division by Recurrence

Abstract

This paper presents the design of a radix-4, 32-bit integer divider which uses a recursive, non-restoring division algorithm. The primary focus for this design is on high-speed operation while maintaining low power consumption. This implementation accepts 32-bit unsigned integers as input, and returns the quotient, remainder, and a special case divide-by-zero flag. Included in this paper is the motivation for this design, background information necessary to understand the algorithm in use, details of the algorithm's implementation, and the evaluation of the proposed design implemented in IBM/GF 32nm SOI technology, which is then compared against other division implementations.