Adaptive Architectural Enhancements for 16-Bit Machine Learning Application-Specific Processors

Abstract

This paper presents architectural enhancements that allow for the use of digital signal processing operations, such as convolution and multiply-and-accumulate operations, that can be applied to machine learning applications on a 16-bit processor while maintaining low power and area consumption. The proposed design focuses on implementing hardware for a type of machine learning called the convolutional neural network. In addition to the convolution and multiply-and-accumulate operations that can be computed with the addition of the proposed architectural enhancements, common case instructions such as multiplication and addition can be utilized with out creating additional hardware. Included in this paper are the motivation for the enhancements, background on the building blocks necessary to modify the processor, the implementation of the architectural enhancements, and the verification and evaluation of the proposed design against other machine learning architectures using simulation and synthesis, respectively.