| dc.description.abstract | Two-step flash architectures are an effective means of realizing high speed, high resolution A/D converters. With conversion rates approaching half those of fully parallel A/D converter's, this type of architecture provides a relatively small input capacitance together with low power dissipation due to the reduced number of comparators required to achieve the high resolution. A two-'step architecture uses a sample and hold circuit together with a high speed NO � D/A coarse quantizer subtraction circuit. As a part of the effort it was determined that the sample and hold circuit requires a 1590 GHz process bandwidth for 10-bit 2.5GHz application. Such a bigh-performance sample and hold function is clearly not feasible with existing CMOS technology and is beyond the scope of this effort. The folding and interpolation architecture, successfully used in high speed and high resolution bipolar A/D converter [1][4], employs considerable fewer comparators than a fully parallel converter and in addition does not require a sample and hold. The result is a high speed, low power dissipation converter with small die area. While incorporating the folding and interpolation scheme with MOS devices, this type converter suffers from an inherent limitation associated with the linearity of velocity saturated MOS devices. The folding factor number is as small as two due to the soft non-linearity of MOSFET differential pair transfer function (see Appendix A). This restriction results in folding CMOS architecture have a large number of comparators and large power consumption as well as matching difficulties. It was also found that the required 2.5GHz bandwidth for a folding architecture with MOS devices is also well beyond the reach of any current process. Neural networks behave essentially like analog nonlinear circuits. Interconnections between neurons (the elementary processing units) permits one to obtain high parallel computational capabilities, which potentially ensure high speed conversion. The Hopfield neural network is one ofthe most popular networks for electronic neural computing due to the simplicity ofthe network architecture and quick convergence in the time domain. Hopfield neural-based NO converters have several advantages over conventional NO converters. For a 10 bit Hopfield A/D converter only 45 neurons and 10 voltage to current converters are required. Thus, this architecture has a significantly smaller area than the fully flash A/D converter which employs 1023 comparators in the 10 bit case. By adjusting the contribution values between the amplifiers with a learning rule, the adaptive A/D converter with linear A/D conversion performance can be made. The adaptability of a neural-based A/D converter can be useful to compensate for initial device mismatches or long-term characteristic drifts. However, the conversion rate performance is constrained by the worst case delay of LSB (Least Significant Bit) when neural-based architecture applies to 8 - 10 bit resolution. The worst case delay happens when the variation of input signal causes the digital output to be changed from 100 ...00 to 011 ... 11, or from 011 ... 11 to 100... 00. Moreover, the great size differences (up to 64 - 256) between neurons used in 8 - 10 bit application makes their matching very difficult to meet the resolution requirements. Therefore, the neural-based converter is suitable for the 4 - 5 bit resolution application and as previously noted has many advantages over the 4-5 bit flash NO converter. | |
