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Power optimization through clock gating standard cells designed for OSU VLSIARCH SKY130 process
(2022-05)
This thesis proposes the integration of a D-Latch based clock gating cell into the OSU VLSIARCH SKY130 standard cell set, for power optimization purposes. In practice, clock gating is highly effective and easy to implement, ...
Implementations of high performance architecture for IEEE 754 compliant floating-point adders
(2020-12)
This thesis presents a direct iteration and implementation on a high per-formance architecture for IEEE 754 floating-point addition. This thesis improves on the previous architecture's implementation in a variety of ...
Floating-point comparator with relu operator for machine learning enhancement
(2021-05)
This article provides various comparator designs that provide comparisons to double, single, half, and bfloat floating-point values as well as provide comparison modes for 32 and 64 bit two's compliment integer encoded ...