| dc.contributor.author | Chen, Ting-Chang | |
| dc.date.accessioned | 2014-04-17T20:09:21Z | |
| dc.date.available | 2014-04-17T20:09:21Z | |
| dc.date.issued | 2005-05-01 | |
| dc.identifier.uri | https://hdl.handle.net/11244/10285 | |
| dc.description.abstract | The purpose of this research is to find a method to estimate the simulation time for a large digital circuit. A sample circuit is simulated and used to predict the simulation time for similar designs. The prediction of the simulation time can be extended to any circuit by finding a reference circuit. The simulation time of a shift register reference circuit has been determined as a function of the number of bits in the circuit and the number of clock cycles simulated. The reference circuit simulation time serves as a lower bound for the simulation time of more complex circuits. | |
| dc.format | application/pdf | |
| dc.language | en_US | |
| dc.publisher | Oklahoma State University | |
| dc.rights | Copyright is held by the author who has granted the Oklahoma State University Library the non-exclusive right to share this material in its institutional repository. Contact Digital Library Services at lib-dls@okstate.edu or 405-744-9161 for the permission policy on the use, reproduction or distribution of this material. | |
| dc.title | Investigation of the Simulation Performance of Verilog for Large Circuits | |
| dc.type | text | |
| osu.filename | Ting-Chang_okstate_0664M_1327.pdf | |
| osu.college | Engineering, Architecture, and Technology | |
| osu.accesstype | Open Access | |
| dc.description.department | School of Electrical & Computer Engineering | |
| dc.type.genre | Thesis | |
