Show simple item record

Design of a Mips Instruction Set Simulator for Multicore Processor Research in Systemc

dc.contributor.advisorJohnson, Louis G.
dc.contributor.authorQayum, Mohammad Abdul
dc.date.accessioned2014-04-17T20:09:08Z
dc.date.available2014-04-17T20:09:08Z
dc.date.issued2010-07-01
dc.identifier.urihttps://hdl.handle.net/11244/10263
dc.description.abstractThe main focus of this thesis is to design a MIPS Instruction Set Simulator (ISS) for multicore computer architecture research. This MIPS ISS is tested thoroughly for each instruction and by long test benches. Usual ISS works in a purely functional way unlike real hardware, this ISS is designed at a level more abstract than RTL but closer to real processor which will be easy to interface with other cores, caches and micro-architectural parts.
dc.formatapplication/pdf
dc.languageen_US
dc.publisherOklahoma State University
dc.rightsCopyright is held by the author who has granted the Oklahoma State University Library the non-exclusive right to share this material in its institutional repository. Contact Digital Library Services at lib-dls@okstate.edu or 405-744-9161 for the permission policy on the use, reproduction or distribution of this material.
dc.titleDesign of a Mips Instruction Set Simulator for Multicore Processor Research in Systemc
dc.typetext
dc.contributor.committeeMemberHutchens, Chris
dc.contributor.committeeMemberAbdolvand, Reza
osu.filenameQayum_okstate_0664M_11058.pdf
osu.collegeEngineering, Architecture, and Technology
osu.accesstypeOpen Access
dc.description.departmentSchool of Electrical & Computer Engineering
dc.type.genreThesis
dc.subject.keywordscycle accurate
dc.subject.keywordsisa
dc.subject.keywordsiss
dc.subject.keywordsmips
dc.subject.keywordsmulticore
dc.subject.keywordssystemc`


Files in this item

Thumbnail
Name:
Qayum_okstate_0664M_11058.pdf
Size:
1.373Mb
Format:
PDF
View/Open

This item appears in the following Collection(s)

Show simple item record