Design and Characterization of a Standard Cell Library for the FREEPDK45 Process

Abstract

The scope of this thesis can be summarized to two aspects. Firstly, to develop a design methodology to do layouts for a standard cell library to ensure no electrical and functional errors occur due to poor design of the cells when an IC is built out of them using CAD tools. The cell library has been built for the FREEPDK45 process following these rules and can be used for testing the emerging architectures in VLSI and research in academic institutions. Secondly, to establish procedures for characterizing a given cell library using Encounter library characterizer tool from Cadence in yielding correct results. The factors that determine the timing of the cells are studied and the setup to yield accurate results for the cell library developed has been presented. This library has been used in building a mixed signal integrated circuit, and the problems in completing the final physical verification (DRC and LVS) have been studied. The Cell library developed for the FREEPDK process has been characterized and abstracted. The library is tested for its structural correctness when input to CAD tools to construct an integrated circuit. The IC built has been verified to be DRC and LVS clean. The design rules established for building standard cell layouts can be used as a reference manual for designing any other library. The process of characterization is automated and made easy by the Encounter library characterizer tool. However, correctly setting up the tool is very important to yield correct results. The factors that determine this setup have been explored and documented which can also be used as a reference for characterizing any given cell library. The problems while doing LVS for an IC with multiple power domains using Calibre tool and the solution to eliminate them have been documented as well.