Logic Restructuring in Wave-pipelined Circuits:an Integer Programming Approach

Abstract

A key issue involved in the design of wave-pipelined circuits is logic restructuring for delay balancing. This thesis gives an Integer Programming [IP] solution to the problem of delay balancing. The IP problem considers the delay associated with every node in the circuit, fan-in associated with the node and fan-out associated with the node. The heuristic technique used is the branch and bound algorithm, that gives the combination of nodes resulting in minimum delay in the circuit. A weighted graph representation of the circuit is used to solve the IP problem. This thesis also highlights the inherent disadvantages involved in using Linear Programming [LP] to solve the same problem. The results are verified using the Simplex LP/IP solver, an optimization software.