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dc.contributor.advisorJohnson, Louis G.
dc.contributor.authorMarpaung, Julius Jonggara R. Hot Marisi
dc.date.accessioned2013-12-10T18:05:50Z
dc.date.available2013-12-10T18:05:50Z
dc.date.issued2012-05
dc.identifier.urihttps://hdl.handle.net/11244/7864
dc.description.abstractScope and Method of Study: To use and improve a new simulation tool that emulates and studies different cache hierarchies and configurations to evaluate the performance of any chosen processor and cache configurations.
dc.description.abstractFindings and Conclusions: Sharing a L2 cache with more than eight processors may reduce performance. Using a shared L3 cache or hierarchical architecture may result in a better performance. The major factor that contributes to the loss of performance is the bus contention. Increasing the size of shared cache does not have a significant impact on performance.
dc.formatapplication/pdf
dc.languageen_US
dc.rightsCopyright is held by the author who has granted the Oklahoma State University Library the non-exclusive right to share this material in its institutional repository. Contact Digital Library Services at lib-dls@okstate.edu or 405-744-9161 for the permission policy on the use, reproduction or distribution of this material.
dc.titlePerformance evaluations for multicore processors
dc.contributor.committeeMemberRamakumar, R.
dc.contributor.committeeMemberScheets, George
dc.contributor.committeeMemberMayfield, Blayne E.
osu.filenameMarpaung_okstate_0664D_11985.pdf
osu.accesstypeOpen Access
dc.type.genreDissertation
dc.type.materialText
dc.subject.keywordscache
dc.subject.keywordsmulticore
dc.subject.keywordsmultilevel
dc.subject.keywordsprocessors
dc.subject.keywordsspec
dc.subject.keywordssystemc
thesis.degree.disciplineElectrical and Computer Engineering
thesis.degree.grantorOklahoma State University


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