dc.contributor.advisor | Johnson, Louis G. | |
dc.contributor.author | Marpaung, Julius Jonggara R. Hot Marisi | |
dc.date.accessioned | 2013-12-10T18:05:50Z | |
dc.date.available | 2013-12-10T18:05:50Z | |
dc.date.issued | 2012-05 | |
dc.identifier.uri | https://hdl.handle.net/11244/7864 | |
dc.description.abstract | Scope and Method of Study: To use and improve a new simulation tool that emulates and studies different cache hierarchies and configurations to evaluate the performance of any chosen processor and cache configurations. | |
dc.description.abstract | Findings and Conclusions: Sharing a L2 cache with more than eight processors may reduce performance. Using a shared L3 cache or hierarchical architecture may result in a better performance. The major factor that contributes to the loss of performance is the bus contention. Increasing the size of shared cache does not have a significant impact on performance. | |
dc.format | application/pdf | |
dc.language | en_US | |
dc.rights | Copyright is held by the author who has granted the Oklahoma State University Library the non-exclusive right to share this material in its institutional repository. Contact Digital Library Services at lib-dls@okstate.edu or 405-744-9161 for the permission policy on the use, reproduction or distribution of this material. | |
dc.title | Performance evaluations for multicore processors | |
dc.contributor.committeeMember | Ramakumar, R. | |
dc.contributor.committeeMember | Scheets, George | |
dc.contributor.committeeMember | Mayfield, Blayne E. | |
osu.filename | Marpaung_okstate_0664D_11985.pdf | |
osu.accesstype | Open Access | |
dc.type.genre | Dissertation | |
dc.type.material | Text | |
dc.subject.keywords | cache | |
dc.subject.keywords | multicore | |
dc.subject.keywords | multilevel | |
dc.subject.keywords | processors | |
dc.subject.keywords | spec | |
dc.subject.keywords | systemc | |
thesis.degree.discipline | Electrical and Computer Engineering | |
thesis.degree.grantor | Oklahoma State University | |