dc.contributor.advisor | Stine, James E. | |
dc.contributor.author | Castellanos, Ivan Dario | |
dc.date.accessioned | 2013-12-10T18:05:45Z | |
dc.date.available | 2013-12-10T18:05:45Z | |
dc.date.issued | 2008-07 | |
dc.identifier.uri | https://hdl.handle.net/11244/7847 | |
dc.description.abstract | Scope and Method of Study: In today's society, decimal arithmetic is growing considerably in importance given its relevance in financial and commercial applications. Decimal calculations on binary hardware significantly impact performance mainly because most systems utilize software to emulate decimal calculations. The introduction of dedicated decimal hardware on the other hand promises the ability to improve performance by two or three orders of magnitude. The founding blocks of binary arithmetic are studied and applied to the development of decimal arithmetic hardware. New findings are contrasted with existent implementations and validated through extensive simulation. | |
dc.description.abstract | Findings and Conclusions: New architectures and a significant study of decimal arithmetic was developed and implemented. The architectures proposed include an IEEE-754 current revision draft compliant floating-point comparator, a study on decimal division, partial product reduction schemes using decimal compressor trees and a final implementation of a decimal multiplier using advanced techniques for partial product generation. The results of each hardware implementation in nanometer technologies are weighed against existent propositions and show improvements upon area, delay, and power. | |
dc.format | application/pdf | |
dc.language | en_US | |
dc.rights | Copyright is held by the author who has granted the Oklahoma State University Library the non-exclusive right to share this material in its institutional repository. Contact Digital Library Services at lib-dls@okstate.edu or 405-744-9161 for the permission policy on the use, reproduction or distribution of this material. | |
dc.title | Analysis and implementation of decimal arithmetic hardware in nanometer CMOS technology | |
dc.contributor.committeeMember | Johnson, Louis G. | |
dc.contributor.committeeMember | Sohoni, Sohum Ashok | |
dc.contributor.committeeMember | Park, Nohpill | |
osu.filename | Castellanos_okstate_0664D_2881.pdf | |
osu.accesstype | Open Access | |
dc.type.genre | Dissertation | |
dc.type.material | Text | |
dc.subject.keywords | decimal arithmetic | |
dc.subject.keywords | vlsi | |
dc.subject.keywords | arithmetic | |
dc.subject.keywords | decimal multiplication | |
dc.subject.keywords | decimal addition | |
dc.subject.keywords | decimal floating-point | |
thesis.degree.discipline | Electrical and Computer Engineering | |
thesis.degree.grantor | Oklahoma State University | |