Layout Design of 32-bit Brent Kung Adder (Cmos Logic)

Abstract

Adders play a key role in the arithmetic circuits. These arithmetic circuits perform operations like addition, subtraction, multiplication, division, parity calculation etc. The performance of the microprocessors mainly depends upon the speed of the response of these arithmetic operations. Apart from the arithmetic operations the adders are also used for calculating the addresses, tables and similar operations. It is also used in digital signal processor (DSP). As adder is the main circuit, the performance depends on its functioning or speed. Improving its performance is the main area of research in VLSI system design. The conventional adders may work well for small number of bits but when the length increases (say 32-bit, 64-bit, 128-bit and so on) the performance of the conventional adders degrades. Thus in industries tree adders or parallel prefix adders are used for arithmetic operations. There are 6 types of tree adders. Here in this work the layout of 32-bit Brent Kung adder is designed and its delay is calculated. The layouts of 16-bit Brent Kung, Sklansky, Kogge Stone adders are also designed and their delays are compared. The critical path for all these tree adders is computed. For designing these layouts the software used is �magic layout tool� and outputs are verified using �IRSIM�. Minimum transistor width (5lambda) is used in these designs.