Power optimization through clock gating standard cells designed for OSU VLSIARCH SKY130 process

Abstract

This thesis proposes the integration of a D-Latch based clock gating cell into the OSU VLSIARCH SKY130 standard cell set, for power optimization purposes. In practice, clock gating is highly effective and easy to implement, making it ideal for standard cell set characterization. The integration of the proposed D-Latch clock gating cell provides a power reduction benefit to any design it is implemented into, though some designs benefit far more than others. Providing a powerful yet simple power optimization cell to the SKY130 cell set helps to improve standard cell performance, as well as final design benchmarks.