Digital Beamforming Applications and Demonstrations of an RF System-on-a-Chip

Abstract

EM phased array system bandwidth is conventionally constrained by the use of phase shifters for beamsteering, which results in beam squint and pulse dispersion of wideband signals. Wideband antenna performance can be achieved through the use of element-level true time delay (TTD) units, but this is often impractical due to the complexities associated with TTD analog devices. The continued improvement of high-speed analog-to-digital converters (ADC) and digital-to-analog converters (DAC) places digital signal conversion at the element level. This allows TTD beamsteering to be accomplished digitally via a combination of integer-sample delays and fractional-sample delay finite impulse response (FIR) filters, enabling support for wideband communication and radar imaging operating modes.

As phased array systems rely on matched channel characteristics, accurate system calibration is paramount for optimum performance. Narrowband systems which implement beamforming via attenuators and phase shifters often employ lookup tables (LUT) containing a set of correction commands to be superimposed on the desired steering operation. These are commonly dependent on current and desired system characteristics, such as operating frequency, steering direction, power level, and/or temperature conditions. In contrast, wideband systems require higher fidelity compensation techniques capable of correcting imbalanced and dispersive channel effects from element-level electronics.

This dissertation examines deterministic and adaptive beamforming techniques and provides solutions to the aforementioned challenges by contributing the development and demonstration of a wideband digital beamformer with equalization on an RF system-on-a-chip (RFSoC). Performance metrics of the testbed match or exceed current publications of RFSoC based demonstrations. The RFSoC is a unique, state-of-the-art, highly integrated device that incorporates a field programmable gate array (FPGA), high speed ADCs and DACs with a system-on-a-chip (SOC) architecture onto the same silicon fabric. As much of the digital and analog RF circuitry is now integrated into a single package, these devices are revolutionizing radar and communication systems, reshaping phased array system design strategies. This enabling technology facilitates the development of compact all-digital arrays, massively increasing the available degrees of freedom in system control, a paradigm shift in industry and engineering communities.

The beamformer testbed is demonstrated on a sub-Nyquist-sampled 1.6 GHz S-band phased array system implemented using a Xilinx 8-channel 4 GSPS RFSoC. To enable TTD digital beamsteering, each channel is compensated via a conjugate symmetric fractional-sample delay FIR filter bank. By modifying the TTD filter structure to support complex coefficients, channel equalization is integrated with the fractional-sample delays to compensate undesired channel characteristics. To confirm the efficacy of this approach, results are provided for uncalibrated and calibrated system operation. Anechoic chamber measurements are presented as well as the FPGA floorplans showing RFSoC device utilization for both uncalibrated and calibrated configurations.