dc.contributor.advisor | Stine, James E. | |
dc.contributor.author | Mathis, Brett | |
dc.date.accessioned | 2021-05-25T20:42:23Z | |
dc.date.available | 2021-05-25T20:42:23Z | |
dc.date.issued | 2020-12 | |
dc.identifier.uri | https://hdl.handle.net/11244/329967 | |
dc.description.abstract | This thesis presents a direct iteration and implementation on a high per-formance architecture for IEEE 754 floating-point addition. This thesis improves on the previous architecture's implementation in a variety of sub-operations required for IEEE 754 floating-point addition, which are focused on directly improving critical path delay performance. A key element of this paper is the introduction of a flagged-prefix adder within the main carry-propagation path of an end-around-carry adder. It also provides detailed documentation for the design of IEEE 754 compliant floating-point adders. This is particularly emphasized for uncommon operations and control logic used throughout floating-point addition, including denormalized numbers and multi-precision logic. The full design for this architecture has support for binary16, binary32, and binary64 operations. The full extended range provided by denormalized IEEE 754 values is supported. It also has conversion support between IEEE 754 and two's complement integer values in either binary16, binary32, or binary64 precision. The performance comparisons shown are synthesis results in cmos32soi 32nm GF technology and ARM-based standard cells. | |
dc.format | application/pdf | |
dc.language | en_US | |
dc.rights | Copyright is held by the author who has granted the Oklahoma State University Library the non-exclusive right to share this material in its institutional repository. Contact Digital Library Services at lib-dls@okstate.edu or 405-744-9161 for the permission policy on the use, reproduction or distribution of this material. | |
dc.title | Implementations of high performance architecture for IEEE 754 compliant floating-point adders | |
dc.contributor.committeeMember | Teague, Keith | |
dc.contributor.committeeMember | Hu, John | |
osu.filename | Mathis_okstate_0664M_16965.pdf | |
osu.accesstype | Open Access | |
dc.type.genre | Thesis | |
dc.type.material | Text | |
dc.subject.keywords | computer architecture | |
dc.subject.keywords | computer arithmetic | |
dc.subject.keywords | floating-point addition | |
dc.subject.keywords | ieee 754 | |
thesis.degree.discipline | Electrical Engineering | |
thesis.degree.grantor | Oklahoma State University | |