Using Carry Increment Adders to Enhance Energy Savings with Spanning-Tree Adder Structures
Abstract
Hybrid adders have provided innovation in the field of digital arithmetic. These designs take the best parts of multiple implementations and improve results in terms of area, delay, or power. This work implements a 64-bit hybrid adder using a spanning-tree structure with the carry increment algorithm. Synthesis results are obtained for 45nm technology and show promising data when compared with an existing hybrid design.
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