Custom Interface for Charge Trap EEPROM Applications

Abstract

Cryptographic attacks and memory observability among DRAM or PROM have drawn researcher's attention. C. Kothandaraman et al. [1] have proposed a secure memory element using charge-trap based transistor for a potential memory application. The charge trapping layer used in this work is HfO2 which is a high-k dielectric. The properties of HfO2 making it superior to replace traditional SiO2 dielectric are brought together. In general, the trend of scaling non-volatile memory is presented and how dielectric thickness effects the gate length is shown using HfO2 as a solution for scaling beyond 45nm node. This work presents an on-chip interface architecture between CPU and secure EEPROM for control and data communication. This architecture allows the secure EEPROM to be embedded with the processing unit preventing interface eavesdropping so that encryption keys can be accessed locally and securely. It is also designed to overcome the cold-boot attacks [2] and side channel attacks [3] employing on-chip implementation and parallel data communication. Based on the literature, the programming voltages are proposed to meet the optimal requirement of data retention and lifetime. Also, future predictions are made on dielectrics and device architecture for continuous scaling. The interface design is implemented in VHDL and validated with secure EEPROM model. The synthesis and simulation results of the design are presented.