Proposal for an analog CMOS median filter system based on neural network architectural principles

Abstract

This thesis summarizes the investigation of a proposed analog electronic CMOS system for performing median filtering. A description of the problem and rational for investigating neural networks are given followed by a review of recent efforts toward solving the median filtering problem in hardware. A review of the major developments in hardware neural networks is also presented followed by the system proposal. A comparator design intended to function as a major building block is presented and analyzed. A description of efforts to accurately model the comparator follows. A Spice macro model simulation was assembled as well as a dedicated Runge-Kutta system level simulation. The two models were used to evaluate the system's performance when asked to perform median filtering on a number of different types of input data sets. Methods for predicting the behavior of the system are proposed and compared to simulation results. Finally, conclusions and suggestions for future investigations are offered based on the reported simulation results. A large amount of time was spent on putting the necessary software in place to do the work that this thesis summarizes. Difficulties with incompatible spice models, curve fitters. pre-production software versions, and communication links between computers abounded. In spite of all these obstacles, some meaningful data was finally generated allowing the conclusion of this effort.