Development of a CMOS IDDq Testing Environment
dc.contributor.author | Burgess, Richard 1. Jr. | |
dc.date.accessioned | 2014-10-01T13:33:24Z | |
dc.date.available | 2014-10-01T13:33:24Z | |
dc.date.issued | 1995-05-01 | |
dc.identifier.uri | https://hdl.handle.net/11244/12699 | |
dc.description.abstract | A majority of defects found in CMOS technology display elevated quiescent current magnitudes but still may pass functionality tests. By monitoring this power supply current, defect coverage can be elevated past the traditional stuck-at-fault coverage. This study provides a test methodology centered around current supply monitoring. By analyzing fabrication data, defect models, built-in current sensors, current and delay estimation, test set generation, and the QTAG standard, a technique is developed for CMOS integrated circuit testing. A built-in current sensor is presented, which through simulation, exhibits fast detection time. Novel techniques to enhance this time are also presented. | |
dc.format | application/pdf | |
dc.language | en_US | |
dc.publisher | Oklahoma State University | |
dc.rights | Copyright is held by the author who has granted the Oklahoma State University Library the non-exclusive right to share this material in its institutional repository. Contact Digital Library Services at lib-dls@okstate.edu or 405-744-9161 for the permission policy on the use, reproduction or distribution of this material. | |
dc.title | Development of a CMOS IDDq Testing Environment | |
dc.type | text | |
osu.filename | Thesis-1995-B955d.pdf | |
osu.accesstype | Open Access | |
dc.type.genre | Thesis |
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OSU Theses [15752]