Proposal for a 3.3V/5V Low Leakage High Temperature Digital Cell Library using Stacked Transistors

Abstract

The objective of this research is to propose a method for developing a low leakage digital cell library capable of performing at extreme temperatures of up to 275C. The leakage current at extreme temperatures is a dominant factor and plays an important role in determining the circuit performance. A method of stacking low threshold voltage NMOS transistors over regular NMOS transistors has proven to reduce the leakage currents at extreme temperatures without much area penalty and loss in performance. The stacked NMOS transistors were fabricated and leakage data was measured on silicon. The 1.3um stacked NMOS device at 3.3 Volts supply voltage and 1.6um stacked NMOS device at 5 Volts supply voltage, had excellent Ion/Ioff ratios at 275C. The stacked NMOS transistors exhibited up to two orders of magnitude improvement in Ion/Ioff ratios over regular threshold NMOS transistors. Three basic combinational gates - Inverter, 3-input NAND and 3-input NOR gates with stacked NMOS transistors were tested on silicon for their Voltage Transfer Characteristic curves and these exhibited very little shift in the switching thresholds at temperatures of 275C compared to identically sized regular NMOS combinational gates.