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dc.contributor.authorTike, Surpriya
dc.date.accessioned2014-04-17T20:09:20Z
dc.date.available2014-04-17T20:09:20Z
dc.date.issued2011-12-01
dc.identifier.urihttps://hdl.handle.net/11244/10284
dc.description.abstractExploiting flexibilities and scope of multi-core architectures for performance enhancement is one of the highly used approaches used by many researchers. However, with increasing dynamic nature of the workloads of everyday computing, even general multi-core architectures seem to just touch an upper limit on the deliverable performance. This has paved way for meticulous consideration of heterogeneous multi-core architectures. Such architectures can be further enhanced, by making the heterogeneity of the cores dynamic in nature. s work proposes techniques, which change configurations of these cores dynamically with workload. Thus, depending on requirements and pre-programmed preferences, each core can arrange itself to be power optimized or speed optimized. In addition, the project has been designed using RTL (Verilog) to provide completely realistic grip on the silicon investment. The project can be simulated using SPEC2000 and SPEC2006 benchmarks, and is completely synthesizable using IBM_LPE library for 65nm (IBM65LPE).
dc.formatapplication/pdf
dc.languageen_US
dc.publisherOklahoma State University
dc.rightsCopyright is held by the author who has granted the Oklahoma State University Library the non-exclusive right to share this material in its institutional repository. Contact Digital Library Services at lib-dls@okstate.edu or 405-744-9161 for the permission policy on the use, reproduction or distribution of this material.
dc.titleTable Driven Adaptive Effectively Heterogeneous Multi-core Architectures
dc.typetext
osu.filenameTike_okstate_0664M_11877.pdf
osu.collegeEngineering, Architecture, and Technology
osu.accesstypeOpen Access
dc.description.departmentSchool of Electrical & Computer Engineering
dc.type.genreThesis
dc.subject.keywordselectrical engineering


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