Extended Models of Silicon On Sapphire transistors for Analog and Digital Design at elevated temperatures (200�C)

Abstract

This work focuses on extending the vendor supplied SOS MOSFET models to suit high temperature (200�C) CMOS circuit design or more specifically accurate simulation. The SPICE parameters required have been extracted through measurement of High Vt and Low Vt NMOS and PMOS transistors on five spatially separated die (6 transistors of each type on each die) on a wafer with a wide range combinations of lengths and widths over the temperature range of interest (120�C to 200�C). Both analog and digital models were extracted and validated. Transistor mismatch (critical to analog design) was characterized as a function of device width and length for NMOS and PMOS. To support high voltage applications e.g. EEPROM read/write, a (Lightly Doped Drain) High voltage LDD SOS MOSFET was developed and its LDD length-specific model was extracted and verified. In section-II circuit techniques suitable for high temperature operation were developed and verified with a sense amplifier (25�C to 200�C) for an 8KX8 Magneto-resistive Random Access Memory.