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dc.contributor.advisorHutchens, Chris
dc.contributor.authorJain, Vibhor
dc.date.accessioned2014-04-17T20:08:41Z
dc.date.available2014-04-17T20:08:41Z
dc.date.issued2008-07-01
dc.identifier.urihttps://hdl.handle.net/11244/10218
dc.description.abstractThe scope of this research work is to develop digital standard cell and I/O cell libraries operable at 5V power supply and operable up to 125�C using Peregrine 0.5um 3.3 V process. Device geometries are selected based on Ion/Ioff ratios at 125�C. The cell schematic, layout and abstracted views are generated for both the libraries The Standard cell and I/O libraries are characterized for timing and power and the characterization data is realized in various formats compatible with logic synthesis and place and route tools. The pads have been tested for robustness to ESD. A tutorial on abstraction of standard cells and IO cells is prepared using the Cadence Abstract Generator.
dc.formatapplication/pdf
dc.languageen_US
dc.publisherOklahoma State University
dc.rightsCopyright is held by the author who has granted the Oklahoma State University Library the non-exclusive right to share this material in its institutional repository. Contact Digital Library Services at lib-dls@okstate.edu or 405-744-9161 for the permission policy on the use, reproduction or distribution of this material.
dc.titleDesign of 5v Digital Standard Cells And I/O Libraries for Military Standard Temperatures
dc.typetext
dc.contributor.committeeMemberJohnson, Louis G.
dc.contributor.committeeMemberZhang, Weili
osu.filenameJain_okstate_0664M_2883.pdf
osu.collegeEngineering, Architecture, and Technology
osu.accesstypeOpen Access
dc.description.departmentSchool of Electrical & Computer Engineering
dc.type.genreThesis


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