Carry-Propagate Free Combinational Multiplier

Abstract

Multipliers are the heart of most digital systems, however, they are quite complex devices. Standard multiplier designs in digital systems use three basic parts to compute a product, which mainly involve creating and adding partial products. Unfortunately, a significant amount of the worst-case delay attributed to larger multipliers stem from carry-propagate adders to compute the final product. This research involves modifying basic parallel multipliers, so that it can compute the final product using a redundant number notation. Using multipliers that use redundant numbers can increase the complexity of multiplication units, however, it can present designs that avoid the final carry-propagate addition. In this thesis, a design is presented that utilizes the Signed Digit notation, which is used to allow redundancy within the numbers, and subsequently avoid the final carry-propagate adder. Results using silicon standard-cell libraries indicate that for multipliers larger than 32 bits, a significant savings using the proposed architecture is shown. Comparisons versus traditional multipliers are presented and compared for analysis.