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Fir filter design for area efficient implementation /
(2005)
In this dissertation, a variable precision algorithm based on sensitivity analysis is proposed for reducing the wordlength of the coefficients and/or the number of nonzero bits of the coefficients to reduce the complexity ...
Multiplierless CSD techniques for high performance FPGA implementation of digital filters.
(2007)
I leverage FastCSD to develop a new, high performance iterative multiplierless structure based on a novel real-time CSD recoding, so that more zero partial products are introduced. Up to 66.7% zero partial products occur ...