Performance limitations in wide superscalar processors
Abstract
Scope and Method of Study: Superscalar processors with wide instruction fetch only results in diminishing performance returns. The aim of this research to find what causes these limitations. In addition, a new cycle-accurate computer architecture simulator - AbaKus - is developed to study and evaluate the performance of the architecture designs. Findings and Conclusions: Eager-Based executions and their designs are tested to overcome the effects of low-accuracy of branch prediction on 38% of the conditional branch instructions. An improvement IPC of 27% on average is shown. However, confidence estimators need improvement on its design logic as they prove critical on the performance of eager-based executions. In addition, the limitation of compilers to extract ILP from the benchmark programs leads to a severe restriction on performance of Superscalar architectures due to data dependencies.
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- OSU Dissertations [11222]