Optimized Efficient Soft-Decision Viterbi Architecture for Application-Specific Processors

Abstract

This thesis provides an efficient implementation of a soft-decision Viterbi decoder implemented in Global Foundries cmos32soi 32nm technology. This architecture utilizes an efficient branch metric (BM) and normalization architecture by using application specific squaring and comparator units. Results indicate a good trade off between area, delay, and power. Compared to a previous implementation, results indicate a significant decrease in area and delay while running in excess of 1 GHz. In addition, when compared with a soft-decision implementation using a traditional multiplier and comparator, significant reductions in area, delay, and power were observed. Results are given based on using ARM-based standard-cells, and energy/power results are based on Hardware-Descriptive Language implementation. Although this architecture uses more area than hard-decision branch metric implementations, soft-decision implementations can decrease the bit error rate two orders of magnitude thus reducing possible retransmit rates, resulting in both increased throughput and transmission rates.